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| november 2010 doc id 17747 rev 1 1/19 AN3245 application note a hardware and software guid e for the stmpe1801 xpander logic? 18-bit enhanced port ex pander with keypad controller introduction the stmpe1801 is a gpio (general purpose input/output) port expander able to interface a main digital asic via a two-line bidirectional bus (i 2 c). it offers the flex ibility to be configured into a 10x8 matrix keypad controller for qwerty keyboards and general purpose inputs/outputs. this document highlights the guidelines and information complementary to the stmpe1801; xpander logic tm 18-bit enhanced port expander with keypad controller , datasheet, which is necessary for the succe ssful design of stmpe1801 in applications. the first part of the document highlights information on the hardware including external components/connectivity, power, etc. the second part of the document focuses on information regarding the software, in which programming sample codes are shown. www.st.com
contents AN3245 2/19 doc id 17747 rev 1 contents 1 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.1 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.2 rstb pin recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.3 intb pin recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 power sequence (fail safe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 gpio output configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 push-pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.2 open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 keypad controller (kpc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4.1 matrix keys and special function keys . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.2 dedicated keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4.3 combination keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4.4 ghost keys handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 key column/row pins external capacitance . . . . . . . . . . . . . . . . . . . . . . . 12 2 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 i2c initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 programming guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 keypad press/release code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.4 key lock with combination keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 hotkey de-bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 power modes transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AN3245 list of figures doc id 17747 rev 1 3/19 list of figures figure 1. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. rstb connectivity recommendation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. rstb connectivity recommendation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. rstb connectivity recommendation 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. gpio push-pull configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. gpio open drain configuration (output low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. gpio open drain configuration (output high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. matrix keys and special function keys configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. dedicated keys configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 10. three simultaneous key presses with ghost key event . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. three simultaneous key presses without ghost key event . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 12. typical programming flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 hardware AN3245 4/19 doc id 17747 rev 1 1 hardware 1.1 external components 1.1.1 typical app lication circuit figure 1. typical application schematic note: recommended connection at rstb is bas ed on the use of baseband/cpu gpio as the control signal. in a typical application, the following external components are required: r1: 10 k pull-up resistor at rstb r2: 2.2 k - 10 k pull-up resistor at intb r3: 2.2 k - 10 k pull-up resistor at scl (it is recommended that vpullup vcc) r4: 2.2 k - 10 k pull-up resistor at sda (it is recommended that vpullup vcc) c1: 100 nf capacitor at vcc ! - v 6 # # 3 # , 3 $ ! ) . 4 " 2 3 4 " ' . $ 6 n 6 3 4 - 0 % 3 $ ! 3 # , ) . 4 " 2 3 4 " 2 2 2 2 # ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n 6 # # 3 # , 3 $ ! ) . 4 " 2 3 4 " ' . $ 6 n 6 3 4 - 0 % 3 $ ! 3 # , ) . 4 " 2 3 4 " 2 2 2 2 # ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y 2 o w + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / ' 0 ) / + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n + e y # o l u m n AN3245 hardware doc id 17747 rev 1 5/19 1.1.2 rstb pin recommendation the following is a few examples of configurations at rstb depending on applications. if a reset delay is desired (recommended) upon power up, an rc delay can be connected to the rstb as shown below. figure 2. rstb connectivity recommendation 1 if external reset assertion is required through cpu/baseband, rstb can be connected to the gpio. the diagram below shows the presence of a weak pull-up resistor assuming cpu/baseband control is open drain. figure 3. rstb connectivity recommendation 2 ! - v 2 3 4 " 6 # # 6 n 6 2 3 4 " 6 # # 3 4 - 0 % am0 8 414v1 r s tb vcc 1.65 v ? 3 .6 v s tmpe1 8 01 cpu control 10 k r s tb vcc cpu control hardware AN3245 6/19 doc id 17747 rev 1 if reset delay and external reset assertion, as shown in case1 and case2 above, are not required, it is recommended to short the rstb pin to vcc through a resistor. figure 4. rstb connectivity recommendation 3 1.1.3 intb pin recommendation the intb pin is programmable to active low or active high. when programmed to active low, a pull-up resistor of 2.2 k -10 k is required. when programmed to active high, a pull-down resistor of 2.2 k - 10 k is required. if the int signal is not in use, it is necessary to pull the intb pin to vcc. 1.2 power sequence (fail safe) all gpio pins of the stmpe1801 are not fail safe . this means that it is necessary to make sure that vcc supply to stmpe1801 is first turned on before driving the gpio inputs. all other pins except gpio are with fail safe structures. it is possible to have these pins pull- up supply on (for scl/sda/intb) or driven (for rstb) before stmpe1801 vcc turns on. 1.3 gpio output configurations the stmpe1801 provides push-pull type of gpio output as is. if open drain gpio outputs are required, it is configurable with a tweak to the software programming routine. see figures 5 , 6 , and 7 . ! - v 2 3 4 " 6 # # 6 n 6 3 4 - 0 % 2 3 4 " 6 # # AN3245 hardware doc id 17747 rev 1 7/19 1.3.1 push-pull set the gpio to output state through the gpio_set_dir (0x19 - 0x1b) register. input path is disabled. output path is enabled in push-pull configuration. figure 5. gpio push-pull configuration 1.3.2 open drain gpio output driven low by stmpe1801 set the gpio to output state through the gpio_set_dir (0x19 - 0x1b) register. input path is disabled. set the output state to low through the gpio_clr (0x13 - 0x15) register. output path is enabled and gpio pin pulled low. figure 6. gpio open drain configuration (output low) gpio output pulled high by external pull-up resistor set the gpio to input state through the gpio_set_dir (0x19 - 0x1b) register. input path is enabled and output path disabled. gpio is pulled high by external pull-up resistor. ! - v / 5 4 0 5 4 ) . 0 5 4 ' 0 ) / x e n a b l e d d i s a b l e d 3 4 - 0 % / 5 4 0 5 4 ) . 0 5 4 ' 0 ) / x e n a b l e d d i s a b l e d 3 4 - 0 % ! - v / 5 4 0 5 4 ) . 0 5 4 e n a b l e d d i s a b l e d % x t e r n a l p u l l u p ' 0 ) / , / 7 ' 0 ) / x 6 # # 3 4 - 0 % / 5 4 0 5 4 ) . 0 5 4 e n a b l e d d i s a b l e d % x t e r n a l p u l l u p ' 0 ) / , / 7 ' 0 ) / x 6 # # 3 4 - 0 % hardware AN3245 8/19 doc id 17747 rev 1 figure 7. gpio open drain configuration (output high) 1.4 keypad controller (kpc) the integrated keypad controller (kpc) in the stmpe1801 is configurable to the following 3 types of keys: 1. up to 10x8 (80) matrix keys 2. up to 8 special function keys 3. up to 4 dedicated keys ! - v / 5 4 0 5 4 ) . 0 5 4 d i s a b l e d e n a b l e d % x t e r n a l p u l l u p ' 0 ) / ( ) ' ( ' 0 ) / x 6 # # 3 4 - 0 % / 5 4 0 5 4 ) . 0 5 4 d i s a b l e d e n a b l e d % x t e r n a l p u l l u p ' 0 ) / ( ) ' ( ' 0 ) / x 6 # # 3 4 - 0 % AN3245 hardware doc id 17747 rev 1 9/19 1.4.1 matrix keys and special function keys the following is the configuration of the maximum 10x8 (80) matrix keys and 8 special function keys. when any of the special function keys are pressed, the matrix keys of the corresponding row are not detected. for example, when special function key 1 (skey1) is pressed and held, all the matrix keys on row 0 (key1- key10) are not detected. please refer to section 1.4.4 for care and handling of ghost keys. figure 8. matrix keys and special function keys configuration ! - v . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ * 3 , 2 & r o x p q * 3 , 2 & r o x p q * 3 , 2 & r o x p q * 3 , 2 & r o x p q * 3 , 2 & r o x p q * 3 , 2 & r o x p q * 3 , 2 & r o x p q * 3 , 2 & r o x p q * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ * 3 , 2 & r o x p q * 3 , 2 & r o x p q . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z * 3 , 2 5 r z . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ 6 . h \ o d l f h s 6 v \ h n [ l u w d 0 i x q f w l r q n h \ v hardware AN3245 10/19 doc id 17747 rev 1 1.4.2 dedicated keys the following is the configuration of the maximum 4 dedicated keys. four of the row inputs (gpio_0, gpio_1, gpio_2, and gpio_3 pins) can be configured as dedicated keys through the setting of dkey0~3 bits of the kpc_ctrl register. the dedicated keys function supports up to 4 simultaneous key presses in the applications. figure 9. dedicated keys configurations 1.4.3 combination keys the 80 matrix keys can be programmed into a 3 combination key which when pressed simultaneously wakes up the keypad controlle r and sends an interrupt to the host system. this feature can be used to implement the AN3245 hardware doc id 17747 rev 1 11/19 figure 10. three simultaneous key presses with ghost key event three simultaneous key presses without ghost key event ? stmpe1801 stores and reports the 3 keys data ? system host reads key coordinates that do not form a 90 corner of a rectangle. system host should recognize the key data as valid ? for implementation of a function with 3 simultaneous key presses (e.g. hardware AN3245 12/19 doc id 17747 rev 1 1.5 key column/row pins external capacitance for enhancement of esd performance, it is possible that external esd protection diodes are connected to the key column and row pins in the application. this, at the same time, results in additional external capacitance loaded at the pins. in order to ensure that the keypad controller scanning not be affected, the maximum recommended external capacitance at the pins is shown below. ? at vcc=1.8 v, recommended maximum external capacitance is 450 pf. ? at vcc=3.6 v, recommended maximum external capacitance is 900 pf. these values are based on the calculation of the internal active pull-up resistance and the shortest kpc scanning time. AN3245 software doc id 17747 rev 1 13/19 2 software 2.1 i 2 c 2.1.1 i 2 c initialization it is recommended to insert the software reset as the first command during initialization before the starting of the i 2 c transaction. 2.2 programming guide figure 12. typical programming flow 2.2.1 initialization the following is an example for device initialization based on standard implementation for keypad, gpio, and hotkey. keypad initializat ion (e.g. 10x8 keypad initialization) writeregister(sys_ctrl, 0x80);//issue sw reset writeregister(kpc_row,0xff); //activate all rows writeregister(kpc_col_low,0xff); //activate all columns writeregister(kpc_col_high,0x03); writeregister(kpc_ctrl_low,0xf0); ! - v 6 e r i f y # h i p ) $ 6 e r s i o n ) $ 3 9 3 ? # 4 2 , n 3 o f t w a r e r e s e t 3 9 3 ? # 4 2 , % n a b l e ! l l # l o c k + e y p a d # o n t r o l l e r # o n f i g u r a t i o n 0 7 - # o n t r o l l e r # o n f i g u r a t i o n ) n t e r r u p t 3 e r v i c e # o n f i g u r a t i o n ' 0 ) / # o n f i g u r a t i o n software AN3245 14/19 doc id 17747 rev 1 //set scan count, no dedicated keys writeregister(int_en_mask_low,0x06); //enable kpc fifo overflow and kpc interrupt readregister(int_sta_low); //clear interrupt status register writeregister(int_ctrl_low,0x01); //active low, level interrupt, enable global interrupt gpio initialization (e.g. gpio low to output, gpio mid to input) writeregister(sys_ctrl, 0x80);//issue sw reset writeregister(gpio_set_dir_low,0xff); //set port to output writeregister(gpio_set_dir_mid,0x00); //set port to input writeregister(gpio_set_dir_high,0x03); //io 16/17 unused,set to output writeregister(int_en_mask_low,0x08); //enable gpio interrupt writeregister(int_en_gpio_mask_mid,0xff); //enable 8-15 input interrupt readregister(int_sta_gpio); //clear all status in gpio status register readregister (int_sta_low); //clear interrupt status register writeregister(int_ctrl_low,0x01); //active low, level interrupt, enable global interrupt hotkey initialization (e.g. setting gpio15 as hotkey) writeregister(gpio_set_dir_msb,0x80); //set gpio15 to input writeregister(gpio_set_re_msb,0x80); //set gpio15 as rising edge trigger writeregister(int_ctrl,0x01); //active low, level interrupt, enable global interrupt 2.2.2 interrupt handling the following is a sample for the device interrupt/hotkey serving routine based on standard implementation. it is necessary to ensure that the host and stmpe1801 interrupt type (active high/low and level/edge detect) are consistent. interrupt service routine on_interrupt int_status = readregister(int_sta_low); //read interrupt status register // gpio interrupt AN3245 software doc id 17747 rev 1 15/19 if( (int_status & 0x08) == 0x08) //check for gpio interrupt { gpio_int_status = readregister(int_sta_gpio, 3); // read gpio int mask if((gpio_int_status[1] & 0x80) == 0x80) // check for int on gpio15 { // handle gpio interrupt } } // keypad interrupt handling routine if( (int_status & 0x02) == 0x02) //kpc interrupt { readarray(kpc_data, 5); // system handles the key data. } if( (int_status&0x04) == 0x04) //kpc fifo overflow { // system handles data overflow } software AN3245 16/19 doc id 17747 rev 1 2.2.3 keypad press/release code key release (key up) code key press (key down) code table 1. key release code col 0 col 1 col 2 col 3 col 4 col 5 col 6 col 7 col 8 col9 row 0 0x80 0x88 0x90 0x98 0xa0 0xa8 0xb0 0xb8 0xc0 0xc8 row 1 0x81 0x89 0x91 0x99 0xa1 0xa9 0xb1 0xb9 0xc1 0xc9 row 2 0x82 0x8a 0x92 0x9a 0xa2 0xaa 0xb2 0xba 0xc2 0xca row 3 0x83 0x8b 0x93 0x9b 0xa3 0xab 0xb3 0xbb 0xc3 0xcb row 4 0x84 0x8c 0x94 0x9c 0xa4 0xac 0xb4 0xbc 0xc4 0xcc row 5 0x85 0x8d 0x95 0x9d 0xa5 0xad 0xb5 0xbd 0xc5 0xcd row 6 0x86 0x8e 0x96 0x9e 0xa6 0xae 0xb6 0xbe 0xc6 0xce row 7 0x87 0x8f 0x97 0x9f 0xa7 0xaf 0xb7 0xbf 0xc7 0xcf table 2. key press code col 0col 1col 2col 3col 4col 5col 6col 7col 8 col9 row 0 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 row 1 0x01 0x09 0x11 0x19 0x21 0x29 0x31 0x39 0x41 0x49 row 2 0x02 0x0a 0x12 0x1a 0x22 0x2a 0x32 0x3a 0x42 0x4a row 3 0x03 0x0b 0x13 0x1b 0x23 0x2b 0x33 0x3b 0x43 0x4b row 4 0x04 0x0c 0x14 0x1c 0x24 0x2c 0x34 0x3c 0x44 0x4c row 5 0x05 0x0d 0x15 0x1d 0x25 0x2d 0x35 0x3d 0x45 0x4d row 6 0x06 0x0e 0x16 0x1e 0x26 0x2e 0x36 0x3e 0x46 0x4e row 7 0x07 0x0f 0x17 0x1f 0x27 0x2f 0x37 0x3f 0x47 0x4f AN3245 software doc id 17747 rev 1 17/19 2.2.4 key lock with combination keys stmpe1801 provides key lock features when a combination key is defined. without a programmed combination key, this feature is not active. once activated all subsequent key presses are ignored. key lock remains until a combination keys press is detected. key lock is enabled when: 1. bit[1] of the kpc_cmd register is written '1' and 2. all keys are released. read back of '1' at bit [1] of the kpc_cmd register only means that the key lock command is active. it doesn't mean that the device has already entered into key lock mode. read back of '0' at bit [1] of the kpc_cmd register means that the key lock command is not active or the device has exited from key lock mode. 2.3 hotkey de-bounce it is possible that a signal from a mechanical connector (e.g. a 3.5 mm earphone jack) is connected to the stmpe1801 input as a hotkey input. in such a case, excessive noise is expected from the hotkey input due to the mechanical movement. stmpe1801 provides a programmable hotkey de-bounce ranging from 30 s to 210 s (sys_ctrl register 0x02). if this is not sufficient, it is also possible to connect the noise input to one of the 4 dedicated keys (gpio_0, gpio_1, gpio_2, and gpio_3 pins) to which de-bounce can be programmed from 10 ms to 127 ms (kpc_ctrl_mid register 0x34). if the above de-bounce is still not sufficient, the host can impl ement the filtering or de- bouncing by polling the status bit in the interrupt status register (0x09). 2.4 power modes transition ta bl e 3 highlights the states of keypad fifo, gpio, interrupt, and pwm during the various power modes: ? operational mode ? hibernation mode ? reset table 3. power modes vs. gpio/keypad/interrupt data operational mode hibernation mode reset (hw, sw, por, general call) keypad configuration and fifo data active sustained (fifo is read and cleared prior to entering hibernation mode) cleared gpio configuration, pin state, and data active sustained cleared interrupt configuration and data active sustained cleared revision history AN3245 18/19 doc id 17747 rev 1 3 revision history table 4. document revision history date revision changes 03-nov-2010 1 initial release. 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